Layout decomposition for double patterning lithography
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning layout decomposition for simultaneous conflict and stitch minimization
Proceedings of the 2009 international symposium on Physical design
A matching based decomposer for double patterning lithography
Proceedings of the 19th international symposium on Physical design
Mask cost reduction with circuit performance consideration for self-aligned double patterning
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Post-routing layer assignment for double patterning
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Self-aligned double patterning decomposition for overlay minimization and hot spot detection
Proceedings of the 48th Design Automation Conference
Layout decomposition for triple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Optimal layout decomposition for double patterning technology
Proceedings of the International Conference on Computer-Aided Design
WISDOM: wire spreading enhanced decomposition of masks in double patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Template-mask design methodology for double patterning technology
Proceedings of the International Conference on Computer-Aided Design
A polynomial time exact algorithm for self-aligned double patterning layout decomposition
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Flexible self-aligned double patterning aware detailed routing with prescribed layout planning
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Proceedings of the 49th Annual Design Automation Conference
Post-routing layer assignment for double patterning with timing critical paths consideration
Integration, the VLSI Journal
Role of design in multiple patterning: technology development, design enablement and process control
Proceedings of the Conference on Design, Automation and Test in Europe
Double-patterning friendly grid-based detailed routing with online conflict resolution
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Fast and scalable parallel layout decomposition in double patterning lithography
Integration, the VLSI Journal
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Double patterning technology (DPT) has emerged as the most hopeful candidate for the next technology node of the ITRS roadmap [1]. The goal of a DPT decomposer is to decompose the entire layout on each layer onto two masks. It assigns two features to different masks if their spacing is less than a predefined threshold. Besides, some features must be sliced and put onto two masks so that there would be a feasible solution for mask assignment. Such slicing will cause stitches that affect yield. So decomposer needs to minimize their number. In this paper, we formulate the DPT decomposition problem as a maximum cut problem. We propose an extremely efficient two-stage decomposition algorithm called GREMA. The first stage of GREMA generates a set of candidate stitches to ensure that feasible solutions exist for DPT decomposition. The second stage uses maximum cut to find the minimal set of stitches. Our decomposer is able to solve much larger realistic design problems. Experiments demonstrated that GREMA achieved great performance on resolving conflicts with greatly reduced runtime.