A graph theoretic technique to speed up floorplan area optimization
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A cost-driven lithographic correction methodology based on off-the-shelf sizing tools
Proceedings of the 40th annual Design Automation Conference
Performance Driven OPC for Mask Cost Reduction
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Design methodology for IC manufacturability based on regular logic-bricks
Proceedings of the 42nd annual Design Automation Conference
Exact combinatorial optimization methods for physical design of regular logic bricks
Proceedings of the 44th annual Design Automation Conference
Layout decomposition for double patterning lithography
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning layout decomposition for simultaneous conflict and stitch minimization
Proceedings of the 2009 international symposium on Physical design
Simultaneous layout migration and decomposition for double patterning technology
Proceedings of the 2009 International Conference on Computer-Aided Design
GREMA: graph reduction based efficient mask assignment for double patterning technology
Proceedings of the 2009 International Conference on Computer-Aided Design
On process-aware 1-D standard cell design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Constrained pattern assignment for standard cell based triple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
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Double patterning lithography (DPL) is the enabling technology for printing in sub-32nm nodes. In the EDA literature, researchers have been focusing on double-exposure double-patterning (DEDP) DPL for printing arbitrary 2D features where the layout decomposition problem for double exposure is an interesting graph coloring problem. But due to overlay errors, it is very difficult for DEDP to print even 1D features. A more promising DPL technology is self-aligned double patterning (SADP) for 1D design. SADP first prints dense lines and then trims away the portions not on the design by a cut mask. The complexity of cut mask is very high, adding to the sky-rocketing manufacturing cost. In this paper we present a mask cost reduction method with circuit performance consideration for SADP. This is the first paper to focus on the mask cost reduction issue for SADP from a design perspective. We simplify the polygons on the cut mask, by formulating the problem as a constrained shortest path problem. Experimental results show that with a set of layouts in 28nm technology, we can largely reduce the complexity of cut polygons, with little impact on performance.