Layout design methodolgies for sub-wavelength manufacturing
Proceedings of the 38th annual Design Automation Conference
Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
A delay budgeting algorithm ensuring maximum flexibility in placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Research directions for coevolution of rules and routers
Proceedings of the 2003 international symposium on Physical design
Toward a methodology for manufacturability-driven design rule exploration
Proceedings of the 41st annual Design Automation Conference
Manufacturing-Aware Physical Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Performance Driven OPC for Mask Cost Reduction
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Design-process integration for performance-based OPC framework
Proceedings of the 45th annual Design Automation Conference
Timing margin evaluation with a simple statistical timing analysis flow
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Performance-based optical proximity correction methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Mask cost reduction with circuit performance consideration for self-aligned double patterning
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Leakage reduction through optimization of regular layout parameters
Microelectronics Journal
Proceedings of the International Conference on Computer-Aided Design
A simple statistical timing analysis flow and its application to timing margin evaluation
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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As minimum feature sizes continue to shrink, patterned features have become significantly smaller than the wavelength of light used in optical lithography. As a result, the requirement for dimensional variation control, especially in critical dimension (CD) 3σ, has become more stringent. To meet these requirements, resolution enhancement techniques (RET) such as optical proximity correction (OPC) and phase shift mask (PSM) technology are applied. These approaches result in a substantial increase in mask costs and make the cost of ownership (COO) a key parameter in the comparison of lithography technologies. No concept of function is injected into the mask flow; that is, current OPC techniques are oblivious to the design intent, and the entire layout is corrected uniformly with the same effort. We propose a novel minimum cost of correction (MinCorr) methodology to determine the level of correction for each layout feature such that prescribed parametric yield is attained with minimum total RET cost. We highlight potential solutions to the MinCorr problem and give a simple mapping to traditional performance optimization. We conclude with experimental results showing that substantial RET costs may be saved while maintaining a given desired level of parametric yield.