A simple statistical timing analysis flow and its application to timing margin evaluation

Authors:
V. Migairou;R. Wilson;S. Engels;Z. Wu;N. Azemard;P. Maurine
Affiliations:
STMicroelectronics Central CAD & Design Solution, Crolles, France;STMicroelectronics Central CAD & Design Solution, Crolles, France;STMicroelectronics Central CAD & Design Solution, Crolles, France;LIRMM, UMR CNRS/Université de Montpellier II, Montpellier, France;LIRMM, UMR CNRS/Université de Montpellier II, Montpellier, France;LIRMM, UMR CNRS/Université de Montpellier II, Montpellier, France
Venue:
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Year:
2007

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Abstract

The increase of within-die variations and design margins is creating a need for statistical design methods. This paper proposes a simple statistical timing analysis method considering the lot to lot process shifts occurring during production. This method is first validated for 90nm and 65nm processes. Finally, this statistical timing analysis is applied on basic ring oscillators to evaluate the timing margins introduced at the design level by the traditional corner based approach.