A path-based methodology for post-silicon timing validation

Authors:
L. Lee;Li-C Wang;T. M. Mak;Kwang-Ting Cheng
Affiliations:
Dept. of ECE, UC-Santa Barbara, Santa Barbara, CA, USA;Dept. of ECE, UC-Santa Barbara, Santa Barbara, CA, USA;Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada;Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
Venue:
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Year:
2004

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Abstract

This work presents a novel path-based methodology for post-silicon timing validation. In timing validation, the objective is to decide if the timing behavior observed from the silicon is consistent with that predicted by the timing model. At the core of our path-based methodology, we propose a framework to obtain the post-silicon path ranking from observing silicon timing behavior. Then, the consistency is determined by comparing the post-silicon path ranking and the pre-silicon path ranking calculated based on the timing model. Our post-silicon ranking methodology consists of two approaches: ranking optimization and path filtering. We discuss the applications of both approaches and their impacts on the path ranking results. For experiments, we utilize a statistical timing simulator that was developed in the past to derive chip samples and we demonstrate the feasibility of our methodology using benchmark circuits.