A probabilistic approach to clock cycle prediction
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Fast statistical timing analysis handling arbitrary delay correlations
Proceedings of the 41st annual Design Automation Conference
STAC: statistical timing analysis with correlation
Proceedings of the 41st annual Design Automation Conference
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
Proceedings of the 42nd annual Design Automation Conference
A path-based methodology for post-silicon timing validation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution
Proceedings of the 45th annual Design Automation Conference
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We present an evaluation method for estimating the lower bound number of Monte Carlo STA trials required to obtain at least one sample which falls within top-k % of its parent population. The sample can be used to ensure that target designs are timing-error free with a predefined probability using the minimum computational cost. The lower bound number is represented as a closed-form formula which is general enough to be applied to other verifications. For validation, Monte Carlo STA was carried out on various benchmark data including ISCAS circuits. The minimum number of Monte Carlo runs determined using the proposed method successfully extracted one or more top-k % delay instances.