Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations

Authors:
Xin Li;Jiayong Le;Mustafa Celik;L. T. Pileggi
Affiliations:
Extreme DA, Palo Alto, CA, USA;Extreme DA, Palo Alto, CA, USA;Extreme DA, Palo Alto, CA, USA;Dept. of Electr. Eng., California Univ., Riverside, CA, USA
Venue:
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Year:
2005

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Abstract

The large-scale process and environmental variations for today's nanoscale ICs are requiring statistical approaches for timing analysis and optimization. Significant research has been recently focused on developing new statistical timing analysis algorithms, but often without consideration for how one should interpret the statistical timing results for optimization. In this paper (Li et al., 2005) we demonstrate why the traditional concepts of slack and critical path become ineffective under large-scale variations, and we propose a novel sensitivity-based metric to assess the "criticality" of each path and/or arc in the statistical timing graph. We define the statistical sensitivities for both paths and arcs, and theoretically prove that our path sensitivity is equivalent to the probability that a path is critical, and our arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples.