First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
STAC: statistical timing analysis with correlation
Proceedings of the 41st annual Design Automation Conference
Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd annual Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical clock skew analysis considering intradie-process variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis of flip-flops considering codependent setup and hold times
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A parametric approach for handling local variation effects in timing analysis
Proceedings of the 46th Annual Design Automation Conference
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A vast literature has been published on Statistical Static Timing Analysis (SSTA), its motivations, its different implementations and their runtime/accuracy trade-offs. However, very limited literature exists ([1]) on the applicability and the usage models of this new technology on real designs. This work focuses on the use of SSTA in real designs and its practical benefits and limitations over the traditional design flow. We introduce two new metrics to drive the optimization: skew criticality and aggregate sensitivity. Practical benefits of SSTA are demonstrated for clock tree analysis, and correct modeling of on-chip-variations. The use of SSTA to cover the traditional corner analysis and to drive optimization is also discussed. Results are reported on three designs implemented on a 90nm technology.