Deployment of Better Than Worst-Case Design: Solutions and Needs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Opportunities and challenges for better than worst-case design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Clock Distribution Architectures: A Comparative Study
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Analyzing timing uncertainty in mesh-based clock architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Use of statistical timing analysis on real designs
Proceedings of the conference on Design, automation and test in Europe
Analysis of deskew signaling via adaptive timing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Process-induced skew variation for scaled 2-D and 3-D ICs
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Autonomous multi-processor-SoC optimization with distributed learning classifier systems XCS
Proceedings of the 8th ACM international conference on Autonomic computing
Effect of process variations in 3D global clock distribution networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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With shrinking cycle times, clock skew has become an increasingly difficult and important problem for high performance designs. Traditionally, clock skew has been analyzed using case-files which cannot model intradie-process variations and hence result in a very optimistic skew analysis. In this paper, we present a statistical skew analysis method to model intradie process variations. We first present a formal model of the statistical clock-skew problem and then propose an algorithm based on propagation of joint probability density functions in a bottom-up fashion in a clock tree. The analysis accounts for topological correlations between path delays and has linear runtime with the size of the clock tree. The proposed method was tested on several large clock-tree circuits, including a clock tree from a large industrial high-performance microprocessor. The results are compared with Monte Carlo simulation for accuracy comparison and demonstrate the need for statistical analysis of clock skew.