Design for Variability in DSM Technologies
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Use of statistical timing analysis on real designs
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 44th annual Design Automation Conference
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting Setup–Hold-Time Interdependence in Static Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Methodology to achieve higher tolerance to delay variations in synchronous circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Iterative timing analysis considering interdependency of setup and hold times
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Utilizing interdependent timing constraints to enhance robustness in synchronous circuits
Microelectronics Journal
Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Hi-index | 0.00 |
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for employing SSTA is the characterization of the setup and hold times of the latches and flip-flops in the cell library. This paper presents a methodology to exploit the statistical codependence of the setup and hold times. The approach comprises of three steps. In the first step, probability mass function (pmf) of codependent setup and hold time (CSHT) contours are approximated with piecewise linear curves by considering the probability density functions of sources of variability. In the second step, pmf of the required setup and hold times for each flip-flop in the design are computed. Finally, these pmf values are used to compute the probability of individual flip-flops in the design passing the timing constraints and to report the overall pass probability of the flip-flops in the design as a histogram. We applied the proposed method to true single phase clocking flip-flops to generate the piecewise linear curves for CSHT. The characterized flip-flops were instantiated in an example design, on which timing verification was successfully performed.