Numerical continuation methods: an introduction
Numerical continuation methods: an introduction
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Efficient AC and noise analysis of two-tone RF circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Numerical Initial Value Problems in Ordinary Differential Equations
Numerical Initial Value Problems in Ordinary Differential Equations
Numerical Recipes in Pascal: The Art of Scientific Computing
Numerical Recipes in Pascal: The Art of Scientific Computing
Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques
Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques
Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Rapid and accurate latch characterization via direct Newton solution of setup/hold times
Proceedings of the conference on Design, automation and test in Europe
NBTI-aware flip-flop characterization and design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Statistical timing analysis of flip-flops considering codependent setup and hold times
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Parallelizing CAD: a timely research agenda for EDA
Proceedings of the 45th annual Design Automation Conference
Latch modeling for statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing modeling of flipflops considering aging effects
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Iterative timing analysis considering interdependency of setup and hold times
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Utilizing interdependent timing constraints to enhance robustness in synchronous circuits
Microelectronics Journal
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Interdependent characterization of latch setup/hold times is a core component of techniques for pessimism reduction via Setup/Hold Interdependence Aware Static Timing Analysis (SHIA-STA) [1], [2]. We present an efficient and novel method for such characterization, by formulating the interdependent setup-hold time problem as an underdetermined nonlinear equation h(τs, τh) = 0, which we derive from the latch's state-transition function. We solve this equation numerically using a Moore-Penrose Newton method. Further, we use null-space information from the Newton's Jacobian matrix to efficiently find constant-clock-to-Q contours (in the setup/hold time plane), via an Euler-Newton curve tracing procedure. We validate the method on TSPC and C2MOS registers, obtaining speedups of more than 20 x over prior approaches while achieving superior accuracy. This speedup increases linearly with the precision with which curve tracing is desired. In view of the importance and large computational expense of latch characterization in industry today, the new technique represents a significant enabling technology for dramatically speeding up industrial timing closure flows.