Computational geometry: an introduction
Computational geometry: an introduction
Rapid and accurate latch characterization via direct Newton solution of setup/hold times
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 44th annual Design Automation Conference
Methodology to achieve higher tolerance to delay variations in synchronous circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Timing modeling of flipflops considering aging effects
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Iterative timing analysis considering interdependency of setup and hold times
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Utilizing interdependent timing constraints to enhance robustness in synchronous circuits
Microelectronics Journal
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A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static timing analysis tool is described. The proposed methodology prevents optimism and reduces unnecessary pessimism, both of which exist due to independent characterization. Furthermore, the tradeoff between interdependent setup and hold times is exploited to significantly reduce slack violations. These benefits are validated using industrial circuits and tools.