Utilizing interdependent timing constraints to enhance robustness in synchronous circuits

Authors:
E. Salman;E. G. Friedman
Affiliations:
Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, NY 11794, USA;Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, USA
Venue:
Microelectronics Journal
Year:
2012

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Abstract

Interdependent setup-hold times are exploited during the design process to improve the robustness of a circuit. Considering this interdependence only during static timing analysis (STA), as demonstrated in the previous work, is insufficient to fully exploit the capabilities offered by interdependence. This result is due to the strong dependence of STA results on the specific circuit, cell library, and operating frequency. Interdependence is evaluated in this paper for several technologies to determine the overall reduction in delay uncertainty rather than improvements in STA. Reducing delay uncertainty produces a more robust synchronous circuit. The increasing efficacy of interdependence in deeply scaled technologies is also demonstrated by investigating the effect of technology scaling on interdependent timing constraints.