Optimal clock skew scheduling tolerant to process variations

Buffered Clock Tree Synthesis with Non-Zero Clock Skew Schedulingfor Increased Tolerance to Process Parameter Variations

Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks

Minimizing sensitivity to delay variations in high-performance synchronous circuits

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Maximizing performance by retiming and clock skew scheduling

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

A practical clock tree synthesis for semi-synchronous circuits

ISPD '00 Proceedings of the 2000 international symposium on Physical design

Cycle time and slack optimization for VLSI-chips

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Clock skew scheduling for improved reliability via quadratic programming

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

UST/DME: a clock tree router for general skew constraints

ACM Transactions on Design Automation of Electronic Systems (TODAES)

UST/DME: a clock tree router for general skew constraints

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Process variation aware clock tree routing

Proceedings of the 2003 international symposium on Physical design

Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip

Discrete Applied Mathematics

Reducing clock skew variability via cross links

Proceedings of the 41st annual Design Automation Conference

Analytical Bound for Unwanted Clock Skew due to Wire Width Variation

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Yield-Driven, False-Path-Aware Clock Skew Scheduling

IEEE Design & Test

A yield improvement methodology using pre- and post-silicon statistical clock scheduling

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Clock schedule verification under process variations

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Skew scheduling and clock routing for improved tolerance to process variations

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Clock Skew Scheduling Under Process Variations

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

Hold time validation on silicon and the relevance of hazards in timing analysis

Proceedings of the 43rd annual Design Automation Conference

ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling

Proceedings of the 43rd annual Design Automation Conference

Clock buffer and wire sizing using sequential programming

Proceedings of the 43rd annual Design Automation Conference

Skew spreading for peak current reduction

Proceedings of the 17th ACM Great Lakes symposium on VLSI

Physical aware clock skew rescheduling

Proceedings of the 17th ACM Great Lakes symposium on VLSI

Optimal useful clock skew scheduling in the presence of variations using robust ILP formulations

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Clock skew scheduling with race conditions considered

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A fast incremental clock skew scheduling algorithm for slack optimization

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

Clock tree synthesis with data-path sensitivity matching

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays

Proceedings of the 45th annual Design Automation Conference

Process variation mitigation via post silicon clock tuning

Proceedings of the 19th ACM Great Lakes symposium on VLSI

Design of voltage overscaled low-power trellis decoders in presence of process variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Clock skew optimization considering complicated power modes

Proceedings of the Conference on Design, Automation and Test in Europe

A study on placement of post silicon clock tuning buffers for mitigating impact of process variation

Proceedings of the Conference on Design, Automation and Test in Europe

Utilizing interdependent timing constraints to enhance robustness in synchronous circuits

Microelectronics Journal

A statistical approach to the timing-yield optimization of pipeline circuits

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation

Revisiting automated physical synthesis of high-performance clock networks

ACM Transactions on Design Automation of Electronic Systems (TODAES)

SmipRef: An efficient method for multi-domain clock skew scheduling

Integration, the VLSI Journal