Optimal clock skew scheduling tolerant to process variations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Statistical skew modeling for general clock distribution networks in presence of process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical clock skew modeling with data delay variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Skewed-Load Transition Test: Part 2, Coverage
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
On Validating Data Hold Times for Flip-Flops in Sequential Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
The Other Side of the Timing Equation: a Result of Clock Faults
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Timing analysis including clock skew
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Clock skew verification in the presence of IR-drop in the power distribution network
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan chain hold-time violations: can they be tolerated
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper we motivate the explicit validation of hold-time violations in silicon and propose a method for doing so. New hold-time failure model and test pattern generation methodologies are defined.We outline conditions under which these tests can be applied reliably. We present results of applying these test patterns on a microprocessor and discuss the implications of intermittent failures on the relevance of hazards during timing analysis.