Worst case clock skew under power supply variations
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Minimum delay optimization for domino logic circuits---a coupling-aware approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analysis of blocking dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hold time validation on silicon and the relevance of hazards in timing analysis
Proceedings of the 43rd annual Design Automation Conference
Silicon speedpath measurement and feedback into EDA flows
Proceedings of the 44th annual Design Automation Conference
A fast and power-area-efficient accumulator for flying-adder frequency synthesizer
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Algorithmic tuning of clock trees and derived non-tree structures
Proceedings of the International Conference on Computer-Aided Design
Multilevel tree fusion for robust clock networks
Proceedings of the International Conference on Computer-Aided Design
Low-power clock trees for CPUs
Proceedings of the International Conference on Computer-Aided Design
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Clock skew is an increasing concern for high-speed circuit designers. Circuit designers use transparent latches and skew-tolerant domino circuits to hide clock skew from the critical path and take advantage of shared portions of the clock network to budget less skew between nearby elements than across the entire die, but current timing analysis algorithms do not handle correlated clock skews. This paper extends the Sakallah-Mudge-Olukotun (SMO) latch-based timing analysis to include different amounts of clock skew between different elements. The key change is that departure times from each latch must be defined with respect to launching clocks so that the skew between the launching and receiving clocks can be determined at each receiver. The exact analysis leads to an explosion in the number of timing constraints, but most constraints are not tight in practical situations and a modified version of the Szymanski-Shenoy relaxation algorithm gives exact results with only a small increase in runtime. The timing analysis formulation also captures the effects of skew on edge-triggered flip-flops, domino circuits, and min-delay constraints. Our exact algorithm, applied to a supercomputer node controller with over 12000 clocked elements, finds the system can run 50-90 ps faster than a single skew analysis would predict and requires searching fewer than 4% more latch departures than conventional algorithms. With the less conservative skew budgets enabled by better timing analysis, we expect clocked systems will remain viable to multi-GHz frequencies