Minimum delay optimization for domino logic circuits---a coupling-aware approach

Authors:
Ki-Wook Kim;Seong-Ook Jung;Taewhan Kim;Sung-Mo Kang
Affiliations:
SiPackets Inc., Santa Clara, CA;T-RAM Inc., San Jose, CA;Korea Advanced Institute of Science & Technology, Taejon, Korea;University of California at Santa Cruz, Santa Cruz, CA
Venue:
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Year:
2003

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Abstract

Minimum delay associated with the hold time requirement is of concern to circuit designers, since race-through hazards are inherent in any multiple clock organization or clock distribution tree irrespective of clock frequency. The monotonic property of domino logic aggravates the min-delay path failure through coupling-induced speedup. To tackle the min-delay problem for domino logic, we propose a min-delay optimization algorithm considering coupling effects. Experimental results indicate that our algorithm yields a significant increase of min-delay without incurring max-delay violation.