RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A crosstalk-aware timing-driven router for FPGAs
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Timing analysis with crosstalk as fixpoints on complete lattice
Proceedings of the 38th annual Design Automation Conference
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
Proceedings of the 38th annual Design Automation Conference
On convergence of switching windows computation in presence of crosstalk noise
Proceedings of the 2002 international symposium on Physical design
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Switching window computation for static timing analysis in presence of crosstalk noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Minimum delay optimization for domino logic circuits---a coupling-aware approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Refining switching window by time slots for crosstalk noise calculation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Method to Estimate Slew and Delay in Coupled Digital Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Timing macro-modeling of IP blocks with crosstalk
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Effects of coupling capacitance and inductance on delay uncertainty and clock skew
Proceedings of the 44th annual Design Automation Conference
A noniterative equivalent waveform model for timing analysis in presence of crosstalk
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A complete and accurate method for static timing analysis of deep sub-micron devices in presence of crosstalk is introduced. This scheme provides an efficient platform for fast and accurate static timing verification of large scale transistor and cell level netlists, with coupled interconnects and high switching speeds. This paper presents the solution to the crosstalk problem implemented in the static timing tool PathMill as its crosstalk extension (CTX). A comparison of simulation results between this approach and SPICE is also provided.