Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
Efficient coupled noise estimation for on-chip interconnects
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
New efficient algorithms for computing effective capacitance
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
TACO: timing analysis with coupling
Proceedings of the 37th Annual Design Automation Conference
Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Timing analysis with crosstalk as fixpoints on complete lattice
Proceedings of the 38th annual Design Automation Conference
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Crosstalk Aware Static Timing Analysis: A Two Step Approach
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Aggressor alignment for worst-case crosstalk noise
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling the “Effective capacitance” for the RC interconnect of CMOS gates
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast bus waveform estimation at the presence of coupling noise
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Fast waveform estimation (FWE) for timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Coupling capacitance has substantial impact on signal delays and arrivaltimes. It is not always correct to de-couple them using the Miller Factors of 0 or 2X.Towards this end various de-coupling techniques have been studied in literature. Weextend them and suggest their use in static timing analysis. Our approach uses theSwitching Factor based de-coupling approximation idea to compute impact of couplingcapacitors on signal slews and delays. We suggest an iterative table lookup scheme.The slew and delay tables for the library cell elements are looked up to compute slewand arrival times of signals in the presence of coupling capacitors. The method iseasy to use with existing static timing analysis tools. It works with slew and delaytables, which are usually available with technology libraries. Other than table lookupsit requires minimal computation of two switching factors per coupling capacitor periteration. Analysis and HSPICE simulation results are given to support the suggestedmethod.