Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
Global harmony: coupled noise analysis for full-chip RC interconnect networks
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient coupled noise estimation for on-chip interconnects
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Efficient Delay Calculation in Presence of Crosstalk
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Coupling Noise Analysis for VLIS and ULSI Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Crosstalk Aware Static Timing Analysis: A Two Step Approach
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing analysis with crosstalk as fixpoints on complete lattice
Proceedings of the 38th annual Design Automation Conference
On convergence of switching windows computation in presence of crosstalk noise
Proceedings of the 2002 international symposium on Physical design
Crosstalk noise optimization by post-layout transistor sizing
Proceedings of the 2002 international symposium on Physical design
Timed pattern generation for noise-on-delay calculation
Proceedings of the 39th annual Design Automation Conference
Efficient switching window computation for cross-talk noise
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Switching window computation for static timing analysis in presence of crosstalk noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Non-iterative switching window computation for delay-noise
Proceedings of the 40th annual Design Automation Conference
Closed-Form Crosstalk Noise Delay Metrics
Analog Integrated Circuits and Signal Processing
A Method to Estimate Slew and Delay in Coupled Digital Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Delay Testing Considering Crosstalk-Induced Effects
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A non-iterative model for switching window computation with crosstalk noise
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Gate delay calculation considering the crosstalk capacitances
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Quantifying Error in Dynamic Power Estimation of CMOS Circuits
Analog Integrated Circuits and Signal Processing
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A variation-aware low-power coding methodology for tightly coupled buses
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A unified framework for statistical timing analysis with coupling and multiple input switching
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Pessimism reduction in crosstalk noise aware STA
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits
Proceedings of the 17th ACM Great Lakes symposium on VLSI
On bounding the delay of a critical path
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
On optimal ordering of signals in parallel wire bundles
Integration, the VLSI Journal
Victim alignment in crosstalk aware timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A noniterative equivalent waveform model for timing analysis in presence of crosstalk
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Fast bus waveform estimation at the presence of coupling noise
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Timing-aware power-optimal ordering of signals
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Overlay aware interconnect and timing variation modeling for double patterning technology
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Constrained aggressor set selection for maximum coupling noise
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Reducing interconnect delay uncertainty via hybrid polarity repeater insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Power-delay optimization in VLSI microprocessors by wire spacing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Victim alignment in crosstalk-aware timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect performance corners considering crosstalk noise
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Semi-random net reordering for reducing timing variations and improving signal integrity
Microelectronics Journal
Switch-factor based loop RLC modeling for efficient timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FA-STAC: An algorithmic framework for fast and accurate coupling aware static timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast waveform estimation (FWE) for timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A dynamic jitter model to evaluate uncertainty trends with technology scaling
Integration, the VLSI Journal
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In coupling delay computation, a Miller factor of more than 2X may be necessary to account for active coupling capacitance when modeling the delay of deep submicron circuitry in the presence of active coupling capacitance. We propose an efficient method to estimate this factor such that the delay response of a decoupling circuit model can emulate the original coupling circuit. Under the assumptions of zero initial voltage, equal charge transfer, and 0.5VDD as the switching threshold voltage, an upper bound of 3X for maximum delay and a lower bound of -1X for minimum delay can be proven. Efficient Newton-Raphson iteration is also proposed as a technique for computing the Miller factor or effective capacitance. This result is highly applicable to crosstalk coupling delay calculation in deep submicron gate-level static timing analysis. Detailed analysis and approximation are presented. SPICE simulations are demonstrated to show high correlation with these approximations.