Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
Chip-level verification for parasitic coupling effects in deep-submicron digital designs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Power estimation for a submicron CMOS inverter driving a CRC interconnect load
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
A rank-one update method for efficient processing of interconnect parasitics in timing analysis
Proceedings of the 37th Annual Design Automation Conference
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Driver modeling and alignment for worst-case delay noise
Proceedings of the 38th annual Design Automation Conference
Osculating Thevenin model for predicting delay and slew of capacitively characterized cells
Proceedings of the 39th annual Design Automation Conference
A library compatible driving point model for on-chip RLC interconnects
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Efficient switching window computation for cross-talk noise
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Explicit gate delay model for timing evaluation
Proceedings of the 2003 international symposium on Physical design
Modeling of Propagation Delay of a First Order Circuit with a Ramp Input
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
An effective capacitance based driver output model for on-chip RLC interconnects
Proceedings of the 40th annual Design Automation Conference
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
A Method to Estimate Slew and Delay in Coupled Digital Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
An Effective Current Source Cell Model for VDSM Delay Calculation
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Driver modeling and alignment for worst-case delay noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new multi-ramp driver model with RLC interconnect load
Proceedings of the 2004 international symposium on Physical design
Equivalent Waveform Propagation for Static Timing Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Gate delay calculation considering the crosstalk capacitances
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Current Calculation on VLSI Signal Interconnects
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Proceedings of the 42nd annual Design Automation Conference
IR Drop and Ground Bounce Awareness Timing Model
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
VGTA: Variation Aware Gate Timing Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Modeling unbuffered latches for timing analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Parameterized block-based non-gaussian statistical gate timing analysis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Predicting short circuit power from timing models
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load
Integration, the VLSI Journal
A nonlinear cell macromodel for digital applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Efficient computation of current flow in signal wires for reliability analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Interconnect modeling for improved system-level design optimization
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Statistical waveform and current source based standard cell models for accurate timing analysis
Proceedings of the 45th annual Design Automation Conference
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Proceedings of the 45th annual Design Automation Conference
A "true" electrical cell model for timing, noise, and power grid verification
Proceedings of the 45th annual Design Automation Conference
Addressing library creation challenges from recent Liberty extensions
Proceedings of the 45th annual Design Automation Conference
Current source based standard cell model for accurate signal integrity and timing analysis
Proceedings of the conference on Design, automation and test in Europe
Fast interconnect and gate timing analysis for performance optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Worst-case aggressor-victim alignment with current-source driver models
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accurate predictive interconnect modeling for system-level design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Current source modeling in the presence of body bias
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools
Microelectronics Journal
Power supply selective mapping for accurate timing analysis
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Compact current source models for timing analysis under temperature and body bias variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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For efficiency, the performance of digital CMOS gates is often expressed in terms of empirical models. Both delay and short-circuit power dissipation are sometimes characterized as a function of load capacitance and input signal transition time. However, gate loads can no longer be modeled by purely capacitive loads for high performance CMOS due to the RC metal interconnect effects. This paper presents a methodology for interfacing empirical gate models to reduced order RC interconnect models in terms of a nonlinear iteration procedure. The delay and power are calculated with errors on the same order as those for the original empirical equations. Moreover, a linear equivalent gate model is generated which accurately captures the delays at the interconnect fan-out nodes