Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Explicit gate delay model for timing evaluation
Proceedings of the 2003 international symposium on Physical design
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
CGTA: current gain-based timing analysis for logic cells
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Constructing Current-Based Gate Models Based on Existing Timing Library
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Cell delay analysis based on rate-of-current change
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Statistical waveform and current source based standard cell models for accurate timing analysis
Proceedings of the 45th annual Design Automation Conference
Current source based standard cell model for accurate signal integrity and timing analysis
Proceedings of the conference on Design, automation and test in Europe
Digital design at a crossroads: how to make statistical design methodologies industrially relevant
Proceedings of the Conference on Design, Automation and Test in Europe
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We present a new approach to model delay of the digital cell in VDSM IC designs. It provides higher accuracy for both delay and transition time than the conventional effective capacitance approximation. The cell is modeled by an effective current source that emulate the behavior of the transistor network. The proposed model is based upon the standard timing tables of the characterized cell.