Numerical recipes in C (2nd ed.): the art of scientific computing
Numerical recipes in C (2nd ed.): the art of scientific computing
A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
An Effective Current Source Cell Model for VDSM Delay Calculation
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Predicting short circuit power from timing models
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Analysis and future trend of short-circuit power
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Characterizing multistage nonlinear drivers and variability for accurate timing and noise analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Current source based standard cell model for accurate signal integrity and timing analysis
Proceedings of the conference on Design, automation and test in Europe
On ATPG for multiple aggressor crosstalk faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Current-based gate modeling achieves a new level of accuracy in nanoscale design timing and signal integrity analysis. However, to generate current-based gate models requires additional pre-characterization of the gate, e.g., in the form of a new or an extended timing library format. We construct current-based gate models based on the existing Liberty timing library format without further pre-characterization. We present an inverse problem formulation, and propose to solve the problem by quadratic polynomial regression. Our constructed current-based gate models find applications in timing, power, and signal integrity verifications for improved accuracy in library-compatible flows, e.g., to include power supply voltage drop effect in gate delay calculation without further pre-characterization, to calculate gate supply current, etc. Our experimental results show our constructed currentbased gate models achieve slightly less accurate results, e.g., within 4.6%(8.6%), than pre-characterized current-based gate models, e.g., within 4.3%(4.4%), of SPICE results in gate delay calculation for ideal (degraded) power supply voltage, and accurate gate supply current calculation.