A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
CMOS gate delay models for general RLC loading
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Driver modeling and alignment for worst-case delay noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Weibull Based Analytical Waveform Model
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Equivalent Waveform Propagation for Static Timing Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
VGTA: Variation Aware Gate Timing Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A Waveform Independent Gate Model for Accurate Timing Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Constructing Current-Based Gate Models Based on Existing Timing Library
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Accurate delay computation for noisy waveform shapes
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
Nonlinear driver models for timing and noise analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Challenges in gate level modeling for delay and SI at 65nm and below
Proceedings of the 45th annual Design Automation Conference
Accurate clock mesh sizing via sequential quadraticprogramming
Proceedings of the 19th international symposium on Physical design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
TinySPICE: a parallel SPICE simulator on GPU for massively repeated small circuit simulations
Proceedings of the 50th Annual Design Automation Conference
Current source modeling for power and timing analysis at different supply voltages
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Nanoscale device characteristics and noise coupling have rendered traditional waveform-based gate delay models increasingly difficult to adopt. While the widely adopted delay models are built upon the assumption of simple ramp-like signal waveforms, realistic signal shapes in nanoscale designs can be far more complex. The need for considering process-voltage-temperature (PVT) variations imposes further accuracy requirement on gate models. We present a parameterizable waveform independent gate model (PWiM) where no assumption is made upon the input waveforms. The PWiM model is constructed by encapsulating the driver's intrinsic nonlinear dc and dynamic characteristics, which are important to model for complex signal waveforms, via novel and yet easy-to-implement characterization steps. As such, PWiM can provide near-SPICE accuracy for input signals that significantly deviate from simple ramps. While recently developed current-based models can only be applied to single channel-connected component, PWiM can work for multistage cells leading to improved library compactness and analysis efficiency. Our experiments have indicated that the proposed driver model not only provides up to two orders of magnitude speedups over SPICE for delay and noise analysis, it also offers accurate assessment of performance variability introduced by process and environmental variations.