IEEE Transactions on Computers
Sizing of clock distribution networks for high performance CPU chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Proceedings of the 37th Annual Design Automation Conference
A multiple level network approach for clock skew minimization with process variations
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Clock Distribution Architectures: A Comparative Study
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Clock buffer and wire sizing using sequential programming
Proceedings of the 43rd annual Design Automation Conference
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Discrete buffer and wire sizing for link-based non-tree clock networks
Proceedings of the 2008 international symposium on Physical design
MeshWorks: an efficient framework for planning, synthesis and optimization of clock mesh networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Characterizing multistage nonlinear drivers and variability for accurate timing and noise analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
A clock power model to evaluate impact of architectural and technology optimizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
General skew constrained clock network sizing based on sequential linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reducing clock skew variability via crosslinks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees
Proceedings of the International Conference on Computer-Aided Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Clock mesh is widely used in microprocessor designs for achieving low clock skew and high variation tolerance. Clock mesh optimization is a very difficult problem because it has highly-connected structure and requires accurate delay models which are computationally expensive. Existing methods on clock network optimization are either restricted to clock trees, which are easy to be separated into smaller problems, or naive heuristics based on crude delay models. In this paper, we propose a clock mesh sizing algorithm which is aimed to minimize mesh wire area with consideration of clock skew constraints. This algorithm is a systematic solution search through rigorous Sequential Quadratic Programming (SQP). The SQP is guided by an efficient adjoint sensitivity analysis which has near-SPICE-level accuracy and faster-than-SPICE speed. Experimental results on various benchmark circuits indicate that our algorithm leads to significant wire area reduction while maintaining low clock skew.