Reliable non-zero skew clock trees using wire width optimization
DAC '93 Proceedings of the 30th international Design Automation Conference
Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Delay-based circuit authentication and applications
Proceedings of the 2003 ACM symposium on Applied computing
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Variational delay metrics for interconnect timing analysis
Proceedings of the 41st annual Design Automation Conference
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Clock Skew Analysis Considering Intra-Die Process Variations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A multiple level network approach for clock skew minimization with process variations
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Statistical Analysis of Clock Skew Variation in H-Tree Structure
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Impact of Interconnect Process Variations on Memory Performance and Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Fast interval-valued statistical interconnect modeling and reduction
Proceedings of the 2005 international symposium on Physical design
VGTA: Variation Aware Gate Timing Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Interval-valued reduced order statistical interconnect modeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Skew scheduling and clock routing for improved tolerance to process variations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Process variation robust clock tree routing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Statistical clock tree routing for robustness to process variations
Proceedings of the 2006 international symposium on Physical design
Statistical Analysis of Capacitance Coupling Effects on Delay and Noise
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
SACI: statistical static timing analysis of coupled interconnects
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Statistical based link insertion for robust clock network design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Analyzing timing uncertainty in mesh-based clock architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 43rd annual Design Automation Conference
Improvement of power distribution network using correlation-based regression analysis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Statistical circuit optimization considering device andinterconnect process variations
Proceedings of the 2007 international workshop on System level interconnect prediction
Worst-case delay analysis considering the variability of transistors and interconnects
Proceedings of the 2007 international symposium on Physical design
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Integrated placement and skew optimization for rotary clocking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient algorithm for statistical circuit optimization using Lagrangian relaxation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Multi-layer interconnect performance corners for variation-aware timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 international workshop on System level interconnect prediction
Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization
Integration, the VLSI Journal
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Novel Method of Interconnect Worstcase Establishment with Statistically-Based Approaches
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation
Proceedings of the 46th Annual Design Automation Conference
Fast statistical analysis of process variation effects using accurate PLL behavioral models
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Accurate clock mesh sizing via sequential quadraticprogramming
Proceedings of the 19th international symposium on Physical design
Interconnect performance corners considering crosstalk noise
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Combinatorial algorithms for fast clock mesh optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock network design for ultra-low power applications
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Understanding the effect of process variations on the delay of static and domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal-aware clock tree design to increase timing reliability of embedded SoCs
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Fast timing analysis of clock networks considering environmental uncertainty
Integration, the VLSI Journal
A parallel and incremental extraction of variational capacitance with stochastic geometric moments
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in today's gigahertz microprocessors can no longer be ignored. Unlike manufacturing variations in the devices, the impact of the interconnect manufacturing variations on IC timing performance cannot be captured by worst/best case corner point methods. Thus it is difficult to estimate the clock skew variability due to interconnect variations. In this paper we analyze the timing impact of several key statistically independent interconnect variations in a context-dependent manner by applying a previously reported interconnect variational order-reduction technique. The results show that the interconnect variations can cause up to 25% clock skew variability in a modern microprocessor design.