Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Proceedings of the 37th Annual Design Automation Conference
Convex delay models for transistor sizing
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Benchmarks for Interconnect Parasitic Resistance and Capacitance
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Process and environmental variation impacts on ASIC timing
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical corner conditions of interconnect delay (corner LPE specifications)
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An IC manufacturing yield model considering intra-die variations
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Worst-case delay analysis considering the variability of transistors and interconnects
Proceedings of the 2007 international symposium on Physical design
Interconnect performance corners considering crosstalk noise
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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Parasitic interconnect corner methods are known to be inaccurate. This paper explains the sources of their errors and shows that errors in excess of 22% can occur in the predicted corner delays of a multi-layer stage in the presence of process variations. It is shown that exhaustive corner search methods are infeasible in practice as they have an exponential complexity in terms of required SPICE simulations with respect to the number of layers a stage is routed through. This exponential complexity is reduced to a linear one with a new simulation-based search method with the aid of stage delay properties. The ideas behind the simulation-based methodology are shown to be expandable to an analytical-based multi-layer performance corner location methodology. The simulated best/worst case delays based on these analytical corners produce errors below 4% as compared to the exhaustive search simulation based method.