A modeling technique for CMOS gates
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Standby power optimization via transistor sizing and dual threshold voltage assignment
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Effective analytical delay model for transistor sizing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Multi-layer interconnect performance corners for variation-aware timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Timing analysis with compact variation-aware standard cell models
Integration, the VLSI Journal
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Journal of Combinatorial Optimization
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This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presented and the circuit delay under such a model is shown to be equivalent to a convex function. The richness of these functions is exploited to accurately model gate delay for modern designs. The delay model is incorporated into a transistor sizing algorithm based on TILOS. The models were characterized by using a set of grid points and then validated using a disjoint data set. The models were found to be within about 10% of SPICE for nearly all of the gate types considered. Also presented are the experimental results of sizing various test circuits.