Convex delay models for transistor sizing
Proceedings of the 37th Annual Design Automation Conference
A new gate delay model for simultaneous switching and its applications
Proceedings of the 38th annual Design Automation Conference
TA-PSV—Timing Analysis for Partially Specified Vectors
Journal of Electronic Testing: Theory and Applications
Output Waveform Evaluation of Basic Pass Transistor Structure
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
A decoupling technique for CMOS strong-coupled structures
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A Parameterizable Fault Simulator for Bridging Faults
ETW '00 Proceedings of the IEEE European Test Workshop
Noise characterization of static CMOS gates
Proceedings of the 41st annual Design Automation Conference
Effective analytical delay model for transistor sizing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Timed input pattern generation for an accurate delay calculation under multiple input switching
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pass transistor operation modeling for nanoscale technologies
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
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In this paper, a modeling technique for CMOS gates, based on the reduction of each gate to an equivalent inverter, is presented. The proposed method can be incorporated in existing timing simulators in order to improve their accuracy. The conducting and parasitic behavior of parallel and serially connected transistors is accurately analyzed and an equivalent transistor is extracted for each case, taking into account the actual operating conditions of each device in the structure. The proposed model incorporates short-channel effects, the influence of body effect and is developed for nonzero transition time inputs. The exact time point when the gate starts conducting is efficiently calculated improving significantly the accuracy of the method. A mapping algorithm for reducing every possible input pattern of a gate to an equivalent signal is introduced and the “weight” of each transistor position in the gate structure is extracted. Complex gates are treated by first mapping every possible structure to a NAND/NOR gate and then by collapsing this gate to an equivalent inverter. Results are validated by comparisons to SPICE and ILLIADS2 for three submicron technologies