Macromodeling of analog circuits for hierarchical circuit design
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
ClariNet: a noise analysis tool for deep submicron design
Proceedings of the 37th Annual Design Automation Conference
Noise propagation and failure criteria for VLSI designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
Static noise analysis with noise windows
Proceedings of the 40th annual Design Automation Conference
A modeling technique for CMOS gates
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Harmony: static noise analysis of deep submicron digital integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 42nd annual Design Automation Conference
TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
| Hi-index | 0.00 |
We present new macromodeling techniques for capturing the response of a CMOS logic gate to noise pulses at the input. Two approaches are presented. The first one is a robust mathematical model which enables the hierarchical generation of noise abstracts for circuits composed of the precharacterized cells. The second is a circuit equivalent model which generates accurate noise waveforms for arbitrarily shaped and timed multiple-input glitches, arbitrary loads, and external noise coupling.