Macromodeling of analog circuits for hierarchical circuit design

Authors:
Jianfeng Shao;Ramesh Harjani
Affiliations:
Department of Electrical Engineering, University of Minnesota, Minneapolis, MN;Department of Electrical Engineering, University of Minnesota, Minneapolis, MN
Venue:
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Year:
1994

Citing 1
Cited 3

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Abstract

Hierarchy plays a significant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. This paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. A modified simplicial approximation technique is used to generate the feasibility macromodel and a layered volume-slicing methodology with radial basis functions is used to generate the performance macromodel. However, due to lack of space, only details of the performance macromodeling techniques are included. Macromodels are developed and verified for analog blocks at three different levels of hierarchy (current mirror, opamp, and A/D converter).