Macromodeling of analog circuits for hierarchical circuit design
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Remembrance of circuits past: macromodeling by data mining in large analog design spaces
Proceedings of the 39th annual Design Automation Conference
Multi-Objective Optimization Using Evolutionary Algorithms
Multi-Objective Optimization Using Evolutionary Algorithms
ASF: a practical simulation-based methodology for the synthesis of custom analog circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Performance trade-off analysis of analog circuits by normal-boundary intersection
Proceedings of the 40th annual Design Automation Conference
HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A CPPLL hierarchical optimization methodology considering jitter, power and locking time
Proceedings of the 43rd annual Design Automation Conference
Pareto-Front Computation and Automatic Sizing of CPPLLs
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
WATSON: design space boundary exploration and model generation for analog and RFIC design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computation of yield-optimized Pareto fronts for analog integrated circuit specifications
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the great lakes symposium on VLSI
| Hi-index | 0.00 |
A new approach in hierarchical optimisation is presented which is capable of optimising both the performance and yield of an analogue design. Performance and yield trade offs are analysed using a combination of multi-objective evolutionary algorithms and Monte Carlo simulations. A behavioural model that combines the performance and variation for a given circuit topology is developed which can be used to optimise the system level structure. The approach enables top-down system optimisation, not only for performance but also for yield. The model has been developed in Verilog-A and tested extensively with practical designs using the Spectre simulator. A performance and variation model of a 5 stage voltage controlled ring oscillator has been developed and a PLL design is used to demonstrate hierarchical optimisation at the system level. The results have been verified with transistor level simulations and suggest that an accurate performance and yield prediction can be achieved with the proposed algorithm.