Feasibility and performance region modeling of analog and digital circuits
Analog Integrated Circuits and Signal Processing - Special issue: modeling and simulation of mixed analog-digital systems
Synthesis tools for mixed-signal ICs: progress on frontend and backend strategies
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the 38th annual Design Automation Conference
An empirical study of evolutionary techniques for multiobjective optimization in engineering design
An empirical study of evolutionary techniques for multiobjective optimization in engineering design
Efficient handling of operating range and manufacturing line variations in analog cell synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
WATSON: design space boundary exploration and model generation for analog and RFIC design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Performance space modeling for hierarchical synthesis of analog integrated circuits
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Yield-aware hierarchical optimization of large analog integrated circuits
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
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A novel methodology is presented to structured yield-aware synthesis. The trade-off between yield and the unspecified performances is explored along the design space boundaries, while respecting specifications on the other performances. Through the unique combination of multi-objective evolutionary optimization techniques, multi-variate regression modeling and sensitivity-based yield estimation, the designer is given access to this trade-off, all within transistor-level accuracy. Even more, a large reduction in required computer resources is obtained compared to alternative approaches.