Practical synthesis of high-performance analog circuits
Practical synthesis of high-performance analog circuits
`` Direct Search'' Solution of Numerical and Statistical Problems
Journal of the ACM (JACM)
Proceedings of the 38th annual Design Automation Conference
A Computer-Aided Design and Synthesis Environment for Analog Integrated Circuits
A Computer-Aided Design and Synthesis Environment for Analog Integrated Circuits
Efficient Global Optimization of Expensive Black-Box Functions
Journal of Global Optimization
Computational Statistics & Data Analysis - Nonlinear methods and data mining
ORACLE: optimization with recourse of analog circuits including layout extraction
Proceedings of the 41st annual Design Automation Conference
HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
OPERA: optimization with ellipsoidal uncertainty for robust analog IC design
Proceedings of the 42nd annual Design Automation Conference
ALPS: the age-layered population structure for reducing the problem of premature convergence
Proceedings of the 8th annual conference on Genetic and evolutionary computation
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Analog Design Centering and Sizing
Analog Design Centering and Sizing
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Analog/RF Circuit Design With Projection-Based Performance Modeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Asymptotic Probability Extraction for Nonnormal Performance Distributions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Two highly efficient second-order algorithms for training feedforward networks
IEEE Transactions on Neural Networks
A holistic approach for statistical SRAM analysis
Proceedings of the 47th Design Automation Conference
Statistical SRAM analysis for yield enhancement
Proceedings of the Conference on Design, Automation and Test in Europe
Hierarchical exact symbolic analysis of large analog integrated circuits by symbolic stamps
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Open-ended evolution to discover analogue circuits for beyond conventional applications
Genetic Programming and Evolvable Machines
Variability aware SVM macromodel based design centering of analog circuits
Analog Integrated Circuits and Signal Processing
Proceedings of the Conference on Design, Automation and Test in Europe
A fast analog circuit yield estimation method for medium and high dimensional problems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A size sensitivity method for interactive CMOS circuit sizing
Analog Integrated Circuits and Signal Processing
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This paper presents SANGRIA, a tool for automated globally reliable variation-aware sizing of analog integrated circuits. Its keys to efficient search are adaptive response surface modeling, and a new concept, structural homotopy. Structural homotopy embeds homotopy-style objective function tightening into the search state's structure, not dynamics. Searches at several different levels are conducted simultaneously: The loosest level does nominal dc simulation, and tighter levels add more analyses and {process, environmental} corners. New randomly generated designs are continually fed into the lowest (cheapest) level, always trying new regions to avoid premature convergence. For further efficiency, SANGRIA adaptively constructs response surface models, from which new candidate designs are optimally chosen according to both yield optimality on model and model prediction uncertainty. The stochastic gradient boosting models support arbitrary nonlinearities, and have linear scaling with input dimension and sample size. SANGRIA uses SPICE in the loop, supports accurate/complex statistical SPICE models, and does not make assumptions about the convexity or differentiability of the objective function. SANGRIA is demonstrated on four different analog circuits having from 10 to 50 devices and up to 444 design/process/environmental variables.