Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic analysis of large-scale networks using a hierarchical signal flowgraph approach
Analog Integrated Circuits and Signal Processing - Special issue on symbolic analysis of analog circuits: techniques and applications
Symbolic Analysis for Automated Design of Analog Integrated Circuits
Symbolic Analysis for Automated Design of Analog Integrated Circuits
Approximate Symbolic Analysis of Hierarchically Decomposed Analog Circuits
Analog Integrated Circuits and Signal Processing
Hierarchical approach to exact symbolic analysis of large analog circuits
Proceedings of the 41st annual Design Automation Conference
A Graph Reduction Approach to Symbolic Circuit Analysis
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A simple implementation of determinant decision diagram
Proceedings of the International Conference on Computer-Aided Design
Canonical symbolic analysis of large analog circuits with determinant decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits
Analog Integrated Circuits and Signal Processing
| Hi-index | 0.00 |
Linearized small-signal transistor models share the common circuit structure but may take different parameter values in the ac analysis of an analog circuit simulator. This property can be utilized for symbolic circuit analysis. This paper proposes to use a symbolic stamp for all device models in the same circuit for hierarchical symbolic analysis. Two levels of binary decision diagrams (BDDs) are used for maximum data sharing, one for the symbolic device stamp and the other for modified nodal analysis. The symbolic transadmittances of the device stamp share one BDD for storage saving. The modified nodal analysis (MNA) matrix formulated using symbolic stamp is of much lower dimension, hence it can be solved by a determinant decision diagram (DDD) with significantly reduced complexity. A circuit simulator is implemented based on the proposed partitioning architecture. It is able to analyze an op-amp circuit containing 44 MOS transistors exactly for the first time.