A Graph Reduction Approach to Symbolic Circuit Analysis

Authors:
Guoyong Shi; Weiwei Chen;C. J. -R. Shi
Affiliations:
Sch. of Microelectron., Shanghai Jiao Tong Univ.;Sch. of Microelectron., Shanghai Jiao Tong Univ.;-
Venue:
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Year:
2007

Citing 0
Cited 3

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Hierarchical exact symbolic analysis of large analog integrated circuits by symbolic stamps

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A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits

Analog Integrated Circuits and Signal Processing

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Abstract

A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed graph reduction process and a recursive sign determination algorithm. A symbolic analog circuit simulator is developed using a combination of these techniques. The simulator is able to analyze large analog circuits in the frequency domain. Experimental results are reported.