Integration, the VLSI Journal
Hierarchical approach to exact symbolic analysis of large analog circuits
Proceedings of the 41st annual Design Automation Conference
A General S-Domain Hierarchical Network Reduction Algorithm
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Compact Reduced Order Modeling for Multiple-Port Interconnects
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Parallel computation of determinants of matrices with polynomial entries for robust control design
Proceedings of the 4th International Workshop on Parallel and Symbolic Computation
Computational complexity analysis of determinant decision diagram
IEEE Transactions on Circuits and Systems II: Express Briefs
Hierarchical exact symbolic analysis of large analog integrated circuits by symbolic stamps
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A simple implementation of determinant decision diagram
Proceedings of the International Conference on Computer-Aided Design
A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits
Analog Integrated Circuits and Signal Processing
Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approach
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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A new method is proposed for hierarchical symbolic analysis of large analog integrated circuits. It consists of performing symbolic suppression of each subcircuit to its terminals in terms of subcircuit matrix determinants and cofactors, and applying Cramer's rule to symbolically solve the set of equations at the top level of the circuit hierarchy. An annotated, directed, and acyclic graph, called determinant decision diagram (DDD), is used to represent symbolic determinants of subcircuit matrices and cofactors used in subcircuit suppression, as well as symbolic determinants of the top-level circuit matrix and cofactors required in applying Cramer's rule. DDD enables us to systematically exploit the inherent sparsity of circuit matrices and the sharing of symbolic expressions. It is capable of representing a huge number of symbolic product terms in a canonical and highly compact manner. The proposed method is illustrated using a Cauer parameter low-pass filter. It has been implemented in a symbolic analyzer and compared to best-known hierarchical symbolic analyzer SCAPP and numerical simulator SPICE. Experimental results on several analog circuits including the μA741 operational amplifier - a circuit with less structural regularities - are described