Multiple-Way Network Partitioning
IEEE Transactions on Computers
Net partitions yield better module partitions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A general purpose multiple way partitioning algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A probability-based approach to VLSI circuit partitioning
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Multiway partitioning with pairwise movement
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Approximate Symbolic Analysis of Hierarchically Decomposed Analog Circuits
Analog Integrated Circuits and Signal Processing
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
An efficient multi-way algorithm for balanced partitioning of VLSI circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Multiway VLSI circuit partitioning based on dual net representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Canonical symbolic analysis of large analog circuits with determinant decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper considers the problem of partitioning analog integrated circuits for hierarchical symbolic analysis based on determinant decision diagrams (DDDs). The objective is to use DDDs with the minimum number of vertices to represent all the symbolic expressions. We show that the problem can be formulated as that of multi-level multi-way hyper graph partitioning with balance constraints, and be solved in two phases by connectivity-oriented initial clustering and iterative improvement. Our new contribution consists of a fast and effective heuristic for constructing a balanced initial partition, a potential gain formulae that can be computed efficiently, and a multiple-vertex moving strategy for relaxing and enforcing balance constraints. The proposed algorithm has been implemented and applied to symbolic analysis of several practical analog integrated circuits. Experimental results are described and compared to the contour tableau method of Sangiovanni-Vincentelli, Chen and Chua, and the SCAPP algorithm of Hassoun and Lin. The resulting hierarchical symbolic analyzer outperforms SPICE in numerical evaluations for a number of large analog circuits.