Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Binary decision diagrams and applications for VLSI CAD
Binary decision diagrams and applications for VLSI CAD
Fast, non-Monte-Carlo estimation of transient performance variation due to device mismatch
Proceedings of the 44th annual Design Automation Conference
Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Programming Massively Parallel Processors: A Hands-on Approach
Programming Massively Parallel Processors: A Hands-on Approach
Canonical symbolic analysis of large analog circuits with determinant decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical approach to exact symbolic analysis of large analog circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we propose a new parallel statistical analysis method for large analog circuits using determinant decision diagram (DDD) based graph technique based on GPU platforms. DDD-based symbolic analysis technique enables exact symbolic analysis of vary large analog circuits. But we show that DDD-based graph analysis is very amenable for massively threaded based parallel computing based on GPU platforms. We design novel data structures to represent the DDD graphs in the GPUs to enable fast memory access of massive parallel threads for computing the numerical values of DDD graphs. The new method is inspired by inherent data parallelism and simple data independence in the DDD-based numerical evaluation process. Experimental results show that the new evaluation algorithm can achieve about one to two order of magnitudes speedup over the serial CPU based evaluations and 2--3 times speedup over numerical SPICE-based simulation method on some large analog circuits.