IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic generation of hierarchical placement rules for analog integrated circuits
Proceedings of the 19th international symposium on Physical design
Analog layout synthesis: recent advances in topological approaches
Proceedings of the Conference on Design, Automation and Test in Europe
Simulation-based analog and RF circuit synthesis using a modified evolutionary strategies algorithm
Integration, the VLSI Journal
Fast analog layout prototyping for nanometer design migration
Proceedings of the International Conference on Computer-Aided Design
Configurable analog routing methodology via technology and design constraint unification
Proceedings of the International Conference on Computer-Aided Design
Operating-point driven formulation for analog computer-aided design
Analog Integrated Circuits and Signal Processing
An axiomatic model for concept structure description and its application to circuit design
Knowledge-Based Systems
A size sensitivity method for interactive CMOS circuit sizing
Analog Integrated Circuits and Signal Processing
A modified gm/ID design methodology for deeply scaled CMOS technologies
Analog Integrated Circuits and Signal Processing
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This paper presents the sizing rules method for basic building blocks in analog CMOS and bipolar circuit design. It consists of the development of a hierarchical library of transistor-pair groups as basic building blocks for analog CMOS and bipolar circuits, the derivation of a hierarchical generic list of constraints that must be satisfied to guarantee the function and robustness of each block, and the development of a reliable automatic recognition procedure of building blocks in a circuit schematic. Sizing rules efficiently capture design knowledge on the technology-specific level of transistor-pair groups. This reduces the effort and improves the resulting quality for analog circuit synthesis. Results of applications like circuit sizing, design centering, response surface modeling, or analog placement show the benefits of the sizing rules method.