A statistical optimization-based approach for automated sizing of analog cells
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Analog Integrated Circuits and Signal Processing - Special issue: low-voltage low-power analog integrated circuits
Automating the sizing of analog CMOS circuits by consideration of structural constraints
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Computer Methods for Circuit Analysis and Design
Computer Methods for Circuit Analysis and Design
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Analog Design Centering and Sizing
Analog Design Centering and Sizing
Electronic Circuit & System Simulation Methods (SRE)
Electronic Circuit & System Simulation Methods (SRE)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches
A new approach to sizing analog CMOS building blocks using pre-compiled neural network models
Analog Integrated Circuits and Signal Processing
Application of statistical design and response surface methods to computer-aided VLSI device design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Canonical symbolic analysis of large analog circuits with determinant decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal design of a CMOS op-amp via geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMOS op-amp sizing using a geometric programming formulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A CAD methodology for optimizing transistor current and sizing in analog CMOS design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pole and zero sensitivity calculation in asymptotic waveform evaluation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits
Analog Integrated Circuits and Signal Processing
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A new device sizing method for CMOS analog integrated circuit is proposed. This method employs graphical sensitivity curves of certain performance metric with respect to device sizes, called size sensitivity, to guide the designer to choose proper device sizes semi-automatically. It is shown that the plot of sensitivity curves in the frequency-domain can exhibit quantitative performance dependence to device sizes nearby dominant pole/zero locations. For accurate sensitivity calculation, the dependence on dc sensitivity in the computation of ac sensitivity to device size is emphasized and an EKV model-based implementation is outlined. The proposed graphical semi-automatic analog sizing methodology differentiates itself from the traditional black-box approaches with which the user has no interference in the optimization process. An interactive semi-automatic analog sizing tool with a graphical interface allows the user to decide which device sizes are more rewarding to tune. An operational amplifier is sized by using the proposed interactive tool.