Simulated annealing: theory and applications
Simulated annealing: theory and applications
Symbolic Analysis for Automated Design of Analog Integrated Circuits
Symbolic Analysis for Automated Design of Analog Integrated Circuits
Synthesis tools for mixed-signal ICs: progress on frontend and backend strategies
DAC '96 Proceedings of the 33rd annual Design Automation Conference
MAELSTROM: efficient simulation-based synthesis for custom analog cells
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
ASF: a practical simulation-based methodology for the synthesis of custom analog circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Synthesis of analog and mixed-signal integrated electronic circuits
Formal engineering design synthesis
Classification of analog synthesis tools based on their architecture selection mechanisms
Integration, the VLSI Journal
Technology independent circuit sizing for standard cell based design using neural networks
Digital Signal Processing
Analog circuits optimization based on evolutionary computation techniques
Integration, the VLSI Journal
Intent-leveraged optimization of analog circuits via homotopy
Proceedings of the Conference on Design, Automation and Test in Europe
Analog Integrated Circuits and Signal Processing
Operating-point driven formulation for analog computer-aided design
Analog Integrated Circuits and Signal Processing
A size sensitivity method for interactive CMOS circuit sizing
Analog Integrated Circuits and Signal Processing
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This paper presents a CAD tool for automated sizing of analog cells using statistical optimization in a simulation based approach. A nonlinear penalty-like approach is proposed to define a cost function from the performance specifications. Also, a group of heuristics is proposed to increase the probability of reaching the global minimum as well as to reduce CPU time during the optimization process. The proposed tool sizes complex analog cells starting from scratch, within reasonable CPU times (approximately 1 hour for a fully differential opamp with 51 transistors), requiring no designer interaction, and using accurate transistor models to support the design choices. Tool operation and feasibility is demonstrated via experimental measurements from a working CMOS prototype of a folded-cascode amplifier.