A statistical optimization-based approach for automated sizing of analog cells
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
ARCHGEN: automated synthesis of analog systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analogue and Mixed-Signal Systems Topologies Exploration Using Symbolic Methods
Analog Integrated Circuits and Signal Processing
GA-SVM feasibility model and optimization kernel applied to analog IC design automation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
The low-frequency distortion in D-class amplifiers
IEEE Transactions on Circuits and Systems II: Express Briefs
An evolutionary approach to automatic synthesis of high-performance analog integrated circuits
IEEE Transactions on Evolutionary Computation
Analog Genetic Encoding for the Evolution of Circuits and Networks
IEEE Transactions on Evolutionary Computation
Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents an optimization methodology for continuous time loop-filters design applied to Class-D amplifiers. The methodology is based on an evolutionary optimization approach which integrates both the topology selection and circuit sizing by automatically generating optimal sized topologies and performance tradeoffs for the Class-D amplifier. The presented approach is demonstrated on two cases: for the design of a half-bridge amplifier and for a fully differential BTL class-D loop filter topology that achieves less than 0.003% THD at 680 mW output power in typical 0.18 μm CMOS technology.