A statistical optimization-based approach for automated sizing of analog cells
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A new approach to sizing analog CMOS building blocks using pre-compiled neural network models
Analog Integrated Circuits and Signal Processing
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This paper presents a neural network (NN) approach for modeling the time characteristics of fundamental gates of digital integrated circuits that include inverter, NAND, NOR, and XOR gates. The modeling approach presented here is technology independent, fast, and accurate, which makes it suitable for circuit simulators. Firstly transient simulations were done in order to obtain delay times for different transistor sizes and different load capacitances using AMIS 1.5 @mm, TSMC 0.25 @mm and TSMC 0.18 @mm technology parameters with HSPICE. These delay time results constitute the inputs of NN while the outputs are transistor sizes. Then, two neural network structures, multilayer perceptron (MLP) and general regression neural network (GRNN), were compared to estimate the transistor sizes. MLP achieved 91 acceptable results through 120 test data where GRNN had 77. The important thing is that the NN is able to generalize the input-output mapping and estimates the outputs for new data which were not applied to the NN for training before. As a conclusion, fundamental gates used for standard cell based VLSI design can be sized for desired delay times using neural networks without knowing SPICE technology parameters.