A new approach to sizing analog CMOS building blocks using pre-compiled neural network models

Authors:
Kaustubha Mendhurwar;Harsh Sundani;Priyanka Aggarwal;Rabin Raut;Vijay Devabhaktuni
Affiliations:
Department of ECE, Concordia University, Montreal, Canada H3G 1M8;EECS Department, MS 308, University of Toledo, Toledo, USA 43606;EECS Department, MS 308, University of Toledo, Toledo, USA 43606;Department of ECE, Concordia University, Montreal, Canada H3G 1M8;EECS Department, MS 308, University of Toledo, Toledo, USA 43606
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2012

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Abstract

There has been a constant endeavor towards improving the available circuit design automation tools to match technological advancements in the electronic industry. However, inadequate research efforts in the analog domain are holding back the exploitation of advanced technologies. A dearth of design expertise in the analog domain is the principal driving force for the growth of Design Automation (DA) tools. Transistor sizing is one of the most crucial steps in the analog IC design. In this paper, we put forward a new computer aided design framework for the sizing of transistors in MOS Integrated Circuit (IC) amplifiers by incorporating powerful modeling capabilities of Artificial Neural Networks (ANN). ANNs have proven to be efficient and accurate modeling tools in several applications. The proposed tool is capable of directly computing transistor related design parameters, of the MOS IC amplifier and associated peripheral circuitry. The proposed tool thus avoids several time-consuming simulations and/or tuning runs at the very bottom level of analog IC amplifier implementation, using a given CMOS process. It also reduces manual intervention in the design process, thus enhancing the automation of the design process. This paper presents design examples of several analog IC functional modules that are developed and verified successfully.