Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
The sizing rules method for analog integrated circuit design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Analog Integrated Circuits and Signal Processing
A Framework for Designing Reusable Analog Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Generalized Simulation-Based Posynomial Model Generation for Analog Integrated Circuits
Analog Integrated Circuits and Signal Processing
Generalized Posynomial Performance Modeling
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Geometric programming for circuit optimization
Proceedings of the 2005 international symposium on Physical design
On the adequate transistor modeling for optimal design of CMOS OTA
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Digital Circuit Optimization via Geometric Programming
Operations Research
Simulation-based reusable posynomial models for MOS transistor parameters
Proceedings of the conference on Design, automation and test in Europe
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Geometric programming with fuzzy parameters in engineering optimization
International Journal of Approximate Reasoning
Classification of analog synthesis tools based on their architecture selection mechanisms
Integration, the VLSI Journal
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Sizing rules for bipolar analog circuit design
Proceedings of the conference on Design, automation and test in Europe
CMOS op-amp power optimization in all regions of inversion using geometric programming
Proceedings of the 21st annual symposium on Integrated circuits and system design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
An automated design approach for CMOS LDO regulators
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A power optimization method for CMOS op-amps using sub-space based geometric programming
Proceedings of the Conference on Design, Automation and Test in Europe
Simulation-based analog and RF circuit synthesis using a modified evolutionary strategies algorithm
Integration, the VLSI Journal
A geometric programming aided knowledge based approach for analog circuit synthesis and sizing
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Proceedings of the 24th symposium on Integrated circuits and systems design
Proceedings of the Conference on Design, Automation and Test in Europe
Modeling and design of CMOS analog circuits through hierarchical abstraction
Integration, the VLSI Journal
A size sensitivity method for interactive CMOS circuit sizing
Analog Integrated Circuits and Signal Processing
| Hi-index | 0.03 |
The problem of CMOS op-amp circuit sizing is addressed here. Given a circuit and its performance specifications, the goal is to automatically determine the device sizes in order to meet the given performance specifications while minimizing a cost function, such as a weighted sum of the active area and power dissipation. The approach is based on the observation that the first order behavior of a MOS transistor in the saturation region is such that the cost and the constraint functions for this optimization problem can be modeled as posynomial in the design variables. The problem is then solved efficiently as a convex optimization problem. Second order effects are then handled by formulating the problem as one of solving a sequence of convex programs. Numerical experiments show that the solutions to the sequence of convex programs converge to the same design point for widely varying initial guesses. This strongly suggests that the approach is capable of determining the globally optimal solution to the problem. Accuracy of performance prediction in the sizing program (implemented in MATLAB) is maintained by using a newly proposed MOS transistor model and verified against detailed SPICE simulation