GPCAD: a tool for CMOS op-amp synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automating the sizing of analog CMOS circuits by consideration of structural constraints
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Practical synthesis of high-performance analog circuits
Practical synthesis of high-performance analog circuits
Proceedings of the 38th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Discrete Mathematics with Applications
Discrete Mathematics with Applications
Analysis and Design of Integrated Circuits
Analysis and Design of Integrated Circuits
VLSI Design for Manufacturing: Yield Enhancement
VLSI Design for Manufacturing: Yield Enhancement
Synthesis of high-performance analog circuits in ASTRX/OBLX
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient handling of operating range and manufacturing line variations in analog cell synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMOS op-amp sizing using a geometric programming formulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst-case analysis and optimization of VLSI circuit performances
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance trade-off analysis of analog circuits by normal-boundary intersection
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Defining Cost Functions for Robust IC Design and Optimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Synthesis of CMOS Analog Cells Using AMIGO
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Invention and creativity in automated design by means of genetic programming
Artificial Intelligence for Engineering Design, Analysis and Manufacturing
Deterministic approaches to analog performance space exploration (PSE)
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Chameleon ART: a non-optimization based analog design migration framework
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Classification of analog synthesis tools based on their architecture selection mechanisms
Integration, the VLSI Journal
Automatic DC operating point computation and design plan generation for analog IPs
Analog Integrated Circuits and Signal Processing
Sizing rules for bipolar analog circuit design
Proceedings of the conference on Design, automation and test in Europe
A novel Alienor-based heuristic for the optimal design of analog circuits
Microelectronics Journal
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2007 EvoWorkshops 2007 on EvoCoMnet, EvoFIN, EvoIASP,EvoINTERACTION, EvoMUSART, EvoSTOC and EvoTransLog: Applications of Evolutionary Computing
A novel heuristic for multi-objective optimization of analog circuit performances
Analog Integrated Circuits and Signal Processing
Analog blocks design automation
WSEAS Transactions on Circuits and Systems
Analog circuit design optimization through the particle swarm optimization technique
Analog Integrated Circuits and Signal Processing
Behavior-level yield enhancement approach for large-scaled analog circuits
Proceedings of the 47th Design Automation Conference
Analog layout synthesis: recent advances in topological approaches
Proceedings of the Conference on Design, Automation and Test in Europe
Massively multi-topology sizing of analog integrated circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Analog Integrated Circuits and Signal Processing
A fast heuristic approach for parametric yield enhancement of analog designs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Hierarchical sizing and biasing of analog firm intellectual properties
Integration, the VLSI Journal
International Journal of Applied Metaheuristic Computing
Fast isomorphism testing for a graph-based analog circuit synthesis framework
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents the sizing rules method for analog CMOS circuit design that consists of: first, the development of a hierarchical library of transistor pair groups as basic building blocks for analog CMOS circuits; second, the derivation of a hierarchical generic list of constraints that must be satisfied to guarantee the function of each block and its reliability with respect to physical effects; and third, the development of an automatic recognition of building blocks in a circuit schematic. The sizing rules method efficiently captures design knowledge on the technology-specific level of transistor pair groups. This reduces the preparatory modeling effort for analog circuit synthesis. Results of industrial applications to circuit sizing, design centering, response surface modeling and analog placement show the significance of the sizing rules method. Sizing rules especially make sure that automatic circuit sizing and design centering lead to technically meaningful and robust results.