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Analog Design Centering and Sizing
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In traditional yield enhancement approaches, a lot of computation efforts have to be paid first to find the feasible regions and the Pareto fronts, which will become a heavy cost for large analog circuits. In order to reduce the computation efforts, this article proposes a fast heuristic approach that tries to finish all iteration steps of the yield enhancement flow at behavior level. First, a novel force-directed Nominal Point Moving (NPM) algorithm is proposed to find a better nominal point without building the feasible regions. Then, an equation-based behavior-level sizing approach is proposed to map the NPM results at performance level to behavior-level parameters. A fast behavior-level Monte Carlo simulation is also proposed to shorten the iterative yield enhancement flow. Finally, using the obtained behavioral parameters as the sizing targets of each subblock, the device sizing time is significantly reduced instead of sizing from the system-level specifications directly. As demonstrated on several analog circuits, this heuristic approach could be another efficient methodology to help designers improve their analog circuits toward better yield.