Performance trade-off analysis of analog circuits by normal-boundary intersection
Proceedings of the 40th annual Design Automation Conference
Modeling and designing high performance analog reconfigurable circuits
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Synthesis of CMOS Analog Cells Using AMIGO
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Deterministic approaches to analog performance space exploration (PSE)
Proceedings of the 42nd annual Design Automation Conference
Performance space modeling for hierarchical synthesis of analog integrated circuits
Proceedings of the 42nd annual Design Automation Conference
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Hierarchical analysis of process variation for mixed-signal systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Performance-centering optimization for system-level analog design exploration
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Top-down heterogeneous synthesis of analog and mixed-signal systems
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A CPPLL hierarchical optimization methodology considering jitter, power and locking time
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
GA-SVM feasibility model and optimization kernel applied to analog IC design automation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Classification of analog synthesis tools based on their architecture selection mechanisms
Integration, the VLSI Journal
Automatic DC operating point computation and design plan generation for analog IPs
Analog Integrated Circuits and Signal Processing
ANTIGONE: Top-down creation of analog-to-digital converter architectures
Integration, the VLSI Journal
A memetic approach to the automatic design of high-performance analog integrated circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Behavior-level yield enhancement approach for large-scaled analog circuits
Proceedings of the 47th Design Automation Conference
Simulation-based analog and RF circuit synthesis using a modified evolutionary strategies algorithm
Integration, the VLSI Journal
A fast heuristic approach for parametric yield enhancement of analog designs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Hierarchical sizing and biasing of analog firm intellectual properties
Integration, the VLSI Journal
BAG: a designer-oriented integrated framework for the development of AMS circuit generators
Proceedings of the International Conference on Computer-Aided Design
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A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization. It follows a hierarchical refinement strategy for more complex cells and is process independent. The sizing is based on an improved equation-based optimization approach, where the circuit behavior is characterized by declarative models that are then converted in a sequential design plan. Supporting tools have been developed to reduce the total effort to set up a new circuit topology in the system's database. The performance-driven layout generation tool guarantees layouts that satisfy all performance constraints. Redesign support is included in the design flow management to perform backtracking in case of design problems. The experimental results illustrate the productiveness and efficiency of the environment for the synthesis and process tuning of frequently used analog cells