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Performance space modeling for hierarchical synthesis of analog integrated circuits
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KES '08 Proceedings of the 12th international conference on Knowledge-Based Intelligent Information and Engineering Systems, Part III
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Fuzzy techniques in analog circuit design
WSEAS Transactions on Circuits and Systems
Yield-aware hierarchical optimization of large analog integrated circuits
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A Genetic Algorithm-Based Multiobjective Optimization for Analog Circuit Design
KES '09 Proceedings of the 13th International Conference on Knowledge-Based and Intelligent Information and Engineering Systems: Part II
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This paper describes key points and experimental validation in the development of a bottom--up hierarchical, multi--objective evolutionary design methodology for analog blocks. The methodology is applied to a continuous--time ΔΣ A/D converter for WLAN applications, to generate a set of Pareto--optimal design solutions. The generated performance tradeoff offers the designer access to a set of optimal design solutions, from which the designer can choose a satisfactory design point according to the performance specifications. The presented method takes advantage of the Pareto--optimal performance solutions of the hierarchical lower--level sub--blocks to generate the overall Pareto--optimal set at system level. The way the lower--level performance tradeoffs are combined and propagated to higher hierarchical levels, is one of the major key points in the bottom--up methodology. The experimental results validate the methodology for a 7--block hierarchical decomposition of a complex high--speed ΔΣ A/D modulator for a WLAN 802.11a/b/g standard.